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Metastability-Containing Synchronization Circuits
weekly lecture slots:
there are no tutorials
In this course, we cover the theory underlying metastability-containing circuits and their application in improving the performance of clock synchronization algorithms. Metastability is an unstable equilibrium state of basic storage elements like latches and flip-flops. One can simply wait for this transient state to disappear with sufficient probability, which is sufficient for many applications. However, in hardware-level synchronization tasks, time is of the essence. In the course, we will discuss how to model metastability in computational logic in a "digital" way by introducing a third logic state. This leads to a new circuit complexity theory as well as interesting challenges arising in the context of applications, both of which will be covered in the course.
No prerequisites other than basic mathematical knowledge are needed. It can be helpful to have knowledge about (electric) circuitry and Boolean logic, but this is not mandatory. The previous courses How to clock your computer and Clock Synchronization and Adversarial Fault Tolerance are NOT prerequisites.
Please register in the CMS system for this course, as we will hand out course material via this platform. Do not forget to register in HISPOS system on time as you cannot take the exam otherwise. The course is open to whoever is interested in the topic, if you cannot register via CMS please contact the teaching assistant Johannes Bund (johannes dot bund at cispa dot de).