We present the first FPGA implementation of a distributed clock synchronization algorithm with sub-nanosecond skews that can tolerate arbitrary faults of individual components. Each of n nodes is equipped with its own quartz oscillator and the nodes broadcast their clock pulses to enable synchronization. The algorithm provably maintains synchronization even if fewer than n/3 nodes exhibit arbitrary faulty behavior. Moreover, aslong as more than 2n/3 nodes remain synchronized, nodes will recover and resynchronize after transient faults. Using 4 boards with Cyclone IV FPGAs, our implementation achieves precision better than 300 ps. This is in accordance with the worst-case precision of 870 ps predicted by theory. Furthermore, our experiments demonstrate that nodes recover from transient faults as described above. Finally, frequency stability of the overall system improved by an order of magnitude.
ISVLSI
2016-09-08
2026-07-28